Why Use Forth on an FPGA?

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The big problem with FPGA’s is how hard they are to debug. A friend says that they take four times as long as a similar software program.  The problem is that you cannot observe what is going on inside of the circuit.  You would have to lead signals out of the design, maybe using jtag, but off chip frequencies are much lower than on-chip frequencies, so you really cannot observe timing problems, which are of course the major problem.  

With a Forth interpreter on the FPGA, you can quickly lead whatever signals you want to the interpreter, process the signals on the chip, at the chip frequencies, and report any aggregated information off the chip at human speeds.  You can quickly change your testing program, at software development speeds, not at FPGA synthesis and download speeds. Design iteration time is a big issue in FPGA development.  The more functionality you can develop at software development speeds, the faster your FPGA design will be completed. 

Why not use a register machine?  Well assembly is too difficult so you would need to compile the programs to C, or use a higher level interpreted language.  Both of which take up way more memory than a Forth program.  Compared to Forth, C has lots of extra code to move things around on the registers.  And the compilers usually put as much as possible inline, to prevent jumps.  That bloats the executable. And memory is scarce on an fPGA.  In contrast, forth is threaded.    Also many of the Forth commands are in hardware, further shrinking the Forth executable.  With C you also have to figure out how to load the compiled program into the FPGA, which requires additional circuitry, which may not be available on smaller chips.  

With this approach,  at the end of the day, you have a Forth interpreter on your chip to do higher level functions so that you do not have to implement them in digital circuits.  For example the NMOS chips do their IO using software programs, not dedicated logic elements. 

An onboard Forth cpu just makes it so much easier to debug your FPGA circuit.  So the killer app for this cpu core is FPGA development.